In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
Integrated circuits include many components, such as transistors, capacitors, and resistors. Resistors are often formed by depositing a conductive line of a particular length within an interlayer dielectric (ILD) layer. The desired resistance of a particular resistor may be set by controlling the length of the conductive line. In some examples, the resistance may be controlled by doping the conductive line with various dopants. Conductive lines, such as those used for resistors, may form capacitive coupling with the substrate below the ILD layer. For example, the substrate may be a p-substrate with an n-well formed therein. The n-well may provide a common capacitive coupling for an array of resistors. This capacitive coupling may limit the use of such resistor arrays. For example, when simulating such circuits, the accuracy of the simulations may only be sufficient if each of the resistors in the array function together rather than individually. It would be desirable to have resistor arrays that do not suffer from such limitations.